It is common practice in the electronics industry to test a circuit board populated with components by launching one or more test signals into the circuit board and then sensing the level of signals returned in response to the launched test signals. When the circuit board is operating properly, the launching of a test signal of known amplitude into the board causes a response signal of known amplitude to be returned. Thus, by monitoring whether each of the response signals returned from the circuit board has an amplitude greater or less than the known amplitude, defects in the circuit board can be detected.
There presently exist electronic circuits for detecting whether an input signal has an amplitude greater or less than a reference voltage of predetermined amplitude. Such circuits are usually referred to as signal or voltage comparators and are often found in automatic testing machines of the type used to test electronic circuit boards in the manner described above. An example of a prior art voltage comparator circuit is found in U.S. Pat. No. 4,461,964 issued on July 24, 1984 to Shiotari.
The Shiotari comparator is comprised of a first MOS FET of the N channel type coupled between a second and third MOS FET of the N and P channel type, respectively, which are coupled to a voltage source and ground. A fourth MOS FET of the N channel type is coupled between a fifth and sixth MOS FET of the N and P channel type, respectively, which are coupled to the voltage source and to ground. The first and fourth FETs are supplied at their respective gate with an input voltage V.sub.I to be sensed, and a reference voltage V.sub.R, respectively, whereas the drain of each of these two FETs is coupled to a separate one of the SET and RESET inputs of an RS flip-flop. The second, third, fifth and sixth FETs are supplied at their gate with a clock pulse .phi.. During the interval that the second, third, fifth and sixth FETs within the Shiotari comparator are rendered conductive, the RS flip-flop produces a logic "high" level signal at the Q output thereof while the amplitude of V.sub.I exceeds the amplitude of V.sub.R. Conversely, if V.sub. R exceeds V.sub.I, then the flip-flop outputs a logic "low" level signal at its Q output. Thus, the Q output of the flip-flop provides an indication of whether V.sub.I exceeds V.sub.R or not.
There are several disadvantages believed to be incurred by the Shiotari comparator circuit. The first is that the MOS-type FETs employed by Shiotari have a relatively low maximum switching speed (&lt;100 MHz). As a consequence, the Shiotari comparator circuit is believed to be unable to reliably sense the amplitude of very high frequency (&gt;100 MHz) response signals returned from a circuit board being supplied with test signals of a frequency greater than 100 MHz. Therefore, the Shiotari comparator circuit is believed to be generally unsuited for use within automatic testing machines for testing circuit boards at very high frequencies.
In an effort to increase the operating frequency of the Shiotari comparator circuit, one might consider substituting GaAs-type FETs for the MOS devices. Yet, the substitution of GaAs-type FETs would not likely significantly raise the opening frequency of the Shiotari comparator. As described, the Shiotari circuit employs both P and N channel MOS devices. Only N channel GaAs-type FETs offer a significant speed advantage and hence, the required use of both N- and P-type GaAs devices in the Shiotari comparator would not afford a significant speed advantage.
A further disadvantage of the Shiotari comparator is that the source of each of th first and fourth FETs is held at ground potential which prevents the comparator from reliably indicating whether V.sub.R exceeds V.sub.I when either is an ECL level signal. Therefore, the Shiotari comparator circuit is limited to sensing the level of TTL and CMOS level signals only. Also, the Shiotari comparator lacks any mechanism for compensating the amplitude of the drain voltage of the first and fourth FETs for variations caused by temperature changes. Changes in temperature can adversely affect the operating parameters of these FETs which can affect the voltage at their drain, thereby affecting the level of the input voltage at the SET and RESET inputs of the flip-flop. As a result, the Q output signal of Shiotari's flip-flop may not truly reflect whether V.sub.R exceeds V.sub.I.